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Artifact: Digital Computer Memory and Circuit Boards, LVDC, Saturn IB/V Guidance, Navigation and Control

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Identifier: A20120010
Artifact Category: Launch Vehicle Hardware
Period of Employment: February 26 1966 to July 15 1975
Manufacturer: International Business Machine(IBM)
NASA Contract Number: NAS8-14000
Spacecraft/Launch Systems: Saturn I/IB,Saturn V
Dimensions: Memory Core: 5.5 W x 6.5 L x 5.7 H (in),Page Card: 4.2 L x 3.1 W x .4 Thickness (in)
Weight: Memory Core: 5 Pounds (est),Page Card: 4 Ounces (est)
Flight Vehicle System or Component: Cautions and Warnings
Program: Apollo
Flown Status: Unflown

Launch Vehicle Digital Computer (LVDC) Memory Module Assembly and Page Assembly Cards produced by International Business Machines (IBM) Corporation, Federal Systems Division, Rockville Maryland under NASA contract number NAS 8-11561. The LVDC was installed within the Saturn IB and Saturn V Instrument Unit (IU) to support prelaunch checkout; navigation, guidance and attitude control; flight sequence control and orbital checkout of vehicle systems. It represented the brains of the SATURN flight control system and for its time, the “state-of-the-art”in computational technology. Refer to a diagram of the LVDC to the left for a depiction of where the Page Assembly and Memory Modules were installed within the computer’s Magnesium-Lithium Chassis.

Logic Page assembly (cards), shown above and to the left, were fabricated from two Multilayer Interconnection Boards bonded back-to-back ( each side labeled "A" and "B" , and comprised the Logic section of the LVDC. Semiconductor chips are mounted on square ceramic wafers (side length 7.5mm) on which interconnecting wiring and film resistors have been deposited by silk screen printing and firing. The devices, called Unit Logic Devices, are soldered to multi-layer interconnection boards. Each multilayer interconnection board has a capacity of 35 Unit Logic Devices. Two multilayer interconnection boards are bonded back-to-back to a supporting metal frame to form a logic page assembly. Multilayer interconnection boards and pages are joined by connectors to a central multilayer printed circuit board.

The Memory Modules are self-contained assemblies with memory timing, drive, inhibit and sensing circuits arranged around the core array. They provided 4,096 word locations (28 bits each) of primary storage in each of up to eight memory modules for 32,789 words (4 memory modules are shown in this collection) and could be operated in either a simplex or duplex mode, as determined by the Memory Control Elements. Simplex operations took full advantage of the available capacity by storing different information in each mode. Duplex operation halved the capacity of the memory but increased its reliability through redundant storage. Each Memory Module operated independently on command from the Memory Control Element. The modules are divided into sixteen sectors, one of which is designated the “Residual”sector. Each sector contained 256 locations, or addresses. Sector selection was identical for each module and address selection was the same for every sector, except the Residual sector. Storage external to the memory is located predominantly in glass delay lines.

The Memory Module assemblies employed Toroidal (donut shaped) ferrite cores as the storage medium, utilizing coincident current addressing and destructive readout techniques. The hand-woven ferrite cores are arrayed in fourteen 128 x 64 magnetic core planes (refer to diagram to the left of this narrative) and can be magnetized in either of two directions. By establishing that a core contained a “1”  when magnetized in one direction and a “0”when magnetized in the opposite direction, the core can be used to store a single bit of a binary number. Core magnetization was achieved by passing a direct current through the X and Y drive lines (copper wire conductors running through each of the cores comprising the magnetic core planes).

The LVDC employed the first computer application and architecture in which all critical circuits were triplicated (triple modular redundancy), giving near-ultimate operative reliability. Designers selected seven functional sections where catastrophic failure might occur but, for reasons of reliability, could not be permitted to occur in flight. Each selected section was then placed in three identical but independent logic channels. Problems were presented to each module simultaneously, and the results of each, independently derived, went to a majority-rule voter circuit. Any dissenting "vote" was discarded as an error, and the only signal passed along by the voter circuit consisted of the identical signals from two of the modules.


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